Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Computationally intensive algorithms such as Deep Neural Networks (DNNs) are becoming killer applications for edge devices. Porting heavily data-parallel on resource-constrained and battery-powered devices while retaining the flexibility granted by instruction processor-based architectures poses several challenges related to memory footprint, computational throughput, energy efficiency. Low-bitwidth mixed-precision arithmetic have been proven be valid strategies tackling these problems. We present Dustin, a fully programmable compute cluster integrating 16 RISC-V cores capable of 2- 32-bit all possible combinations. In addition conventional Multiple-Instruction Multiple-Data (MIMD) processing paradigm, Dustin introduces Vector Lockstep Execution Mode (VLEM) minimize power consumption in highly kernels. VLEM, single leader core fetches instructions broadcasts them 15 follower cores. Clock gating Instruction Fetch (IF) stages private caches leads 38% reduction. The cluster, implemented 65 nm CMOS technology, achieves peak performance 58 GOPS efficiency 1.15 TOPS/W.